In deep sub-micron integrated circuit technology, non-volatile memory device has become a popular storage unit due to various advantages. Particularly, the data saved in the non-volatile memory device are not lost when the power is turned off. One particular example of the non-volatile memory device includes a single floating gate to retain the electrical charges associated with the saved data. When complementary metal-oxide-semiconductor field effect transistor (CMOSFET) technology is implemented, the single floating gate NVM is designed to include a field-effect transistor in a p-type well and a capacitor in a n-type well. However, the capacitor has low coupling efficiency and occupies a large circuit area, leading to large memory cell size and low cell-density. Therefore, a structure of the single non-volatile memory device and a method making the same are needed to address the above issue.